FIG. 1A (Prior Art) is a diagram of an SRAM memory cell 1. Cell 1 includes two pullup resistors 2 and 3 and four transistors 4, 5, 6, and 7 and is therefore commonly referred to as a "4T cell". In operation, digital information is stored in the cell on storage nodes 8 and 9. Consider the example in which a digital low voltage VL is present on node 8 and a digital high voltage VH is present on node 9.
Under static (not read or write) conditions, the low voltage VL on node 8 maintains N-channel pulldown transistor 5 off. Because N-channel access transistor 7 is maintained off due to the digital low (0 volts) present on the word line WL, pull up resistor 3 is adequate to pullup the voltage on storage node 9 to digital high voltage VH. The digital low on word line WL also maintains N-channel access transistor 6 off. The digital high voltage VH on node 9 maintains N-channel pulldown transistor 4 on such that transistor 4 draws an adequate current through pullup resistor 2 such that node 8 is pulled down to low digital voltage VL.
To increase immunity to noise, it is desirable that the cell maintain a significant charge. Alpha particles passing through a cell may generate electron hole pairs in the silicon. Such electron hole pairs may result in an undesirable charge being supplied onto nodes 8 and 9 which is opposite to the information stored on those nodes. If this undesirable charge is great enough, the information stored in the cell may be changed. The charge stored in the cell is approximated by the difference of the voltages VH and VL under static conditions multiplied by the capacitance between storage nodes. It can therefore be seen that maintaining a high Vcc is important to maintaining a high cell charge because a higher Vcc implies a higher VH-VL.
For stability during a read operation, a quantity called the "cell ratio" is important. Again, information is stored in the cell as a difference between VH and VL. To read this information from the cell, bit lines BL1 and BL2 are precharged to Vcc. Once precharged, a digital high (Vcc) is placed on the word line WL so that access transistors 6 and 7 are conductive. In the situation where a digital logic low (0 volts) is present on node 8, the voltage on node 8 rises when access transistor 6 turns on due to a current flow 10. A voltage divider effect occurs due to the on resistances of the two series-connected transistors 6 and 4. This rise in VL is undesirable because the information stored is a difference between VH and VL. It can be seen that maximizing the ratio (i.e. "cell ratio") of the on resistance of access transistor 6 to pulldown transistor 4 minimizes this undesirable rise in VL.
The conductance of access transistor 6 is proportional to Vg6 (gate voltage of transistor 6) minus Vt6 (VSB=VL) (threshold voltage of transistor 6 when the source-to-bulk voltage is equal to VL). FIG. 1B illustrates how threshold voltage changes as a function of source-to-bulk voltage. The bulk (the Pwell) is coupled to the sources of N-channel pulldown transistors 4 and 5. The conductance of pulldown transistor 4 is proportional to Vg4 (the voltage on the gate of transistor 4) minus Vt4 (the threshold voltage of transistor 4 when VSB=0). The voltage on the gate of transistor 4 is, however, VH due to the interconnection of nodes in the cell. The gate voltage of transistor 6 is the word line voltage which is Vcc. The "cell ratio" is therefore approximately: ##EQU1## In equation 1, Tox6 and Tox4 are the thicknesses of the gate oxides of transistors 6 and 4, respectively.
Over time, due to subthreshold leakage of pulldown transistor 5, the voltage VH settles to Vwl (the voltage on the word line) minus Vt7 (the threshold voltage of access transistor 7 when the source-to-bulk voltage is equal to VH). The word line voltage is Vcc. The "cell ratio" is therefore rewritten: ##EQU2## It is therefore seen that Vcc should be maintained as high as possible in order to maintain a high "cell ratio" and preserve cell stability.
With the above cell stability concerns in mind, it is desired to shrink the size of the SRAM cell. Reducing the gate lengths of the transistors 4-7 while maintaining a high Vcc may, however, give rise to other problems. Hot carriers can be injected into the gate oxides of the transistors due to large electric fields, thereby degrading transistor gate oxide quality over time. Punch through problems due to large source-drain electric fields may result in catastrophic failure of transistors in the cell. Undesirable bumpy surface topographies may result due to the thick field oxide required to isolate the large voltages in the cell being confined to smaller spaces.
Reduction of the size of the SRAM cell is therefore limited due to an inability to reduce Vcc without compromising cell stability.